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Wireless Components
TV Mixer-Oscillator-PLL TUA 6010XS Version 1.0
Specification August 1999
preliminary
Revision History: Current Version: 08.99 Previous Version:Data Sheet Page (in previous Version) Page (in current Version) Subjects (major changes since last revision)
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TUA 6010XS
preliminary
Product Info
Product Info
General Description The TUA 6010XS device combines a Package digitally programmable phase locked loop (PLL), with a mixer-oscillator block including two balanced mixers and oscillators for use in TV tuners.
s
Features
PLL with short lock-in time; no asynchronous divider stage Fast I2C bus mode possible 4 programmable chip addresses Short pull-in time for quick channel access and optimized loop stability 3 high-current switch outputs 2 TTL inputs 5-level A/D converter Lock-in flag Power-down flag Few external components Frequency and amplitude-stable balanced oscillator for the VHF, HYPER and UHF frequency range Optimum decoupling of input frequency from oscillator The IC is suitable for all tuners in TV- and VCR-sets or cable set-top receivers for analog TV an Digital Video Broadcasting.
s s s
s s s
s s s s s s s
Double balanced mixer with wide dynamic range and low-impedance inputs for the VHF, HYPER and UHF frequency range Internal band switch Internal low-noise reference voltage source Package TSSOP 28 Full ESD protection
s
s s
Application
s
Ordering Information
Type TUA 6010 XS Ordering Code Package P-TSSOP-28-1
Q67007-A5211
Wireless Components
Product Info
Specification, August 1999
1
Table of Contents
1 2 2.1 2.2 2.3 2.4 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 4 4.1 4.2 5 5.1 5.1.1 5.1.2 5.1.3 5.2 5.3 5.4 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Mixer-Oscillator block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Bit Allocation Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
2
Product Description
Contents of this Chapter 2.1 2.2 2.3 2.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TUA 6010XS
preliminary
Product Description
2.1 Overview
The TUA 6010XS device combines a digitally programmable phase locked loop (PLL), with a mixer-oscillator block including two balanced mixers and oscillators for use in TV tuners. The PLL block with four hard-switched chip addresses forms a digitally programmable phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise setting of the frequency of the tuner oscillator up to 900 MHz in increments of 62.5 kHz. The tuning process is controlled by a microprocessor via an I2C bus. The device has three output ports, which all can also be used as input ports (two TTL inputs and one A/D converter input). A flag is set when the loop is locked. The input ports and lock flag can be read by the processor via the I2C bus. The mixer-oscillator block includes two balanced mixers (double balanced mixer with low-impedance input), two frequency and amplitude-stable balanced oscillators for VHF, HYPER and UHF, a low-noise reference voltage source and a band switch.
2.2 Features
s s s s s s s s s s s
PLL with short lock-in time; no asynchronous divider stage Fast I2C bus mode possible 4 programmable chip addresses Short pull-in time for quick channel access and optimized loop stability 3 high-current switch outputs 2 TTL inputs 5-level A/D converter Lock-in flag Power-down flag Few external components Frequency and amplitude-stable balanced oscillator for the VHF, HYPER and UHF frequency range Optimum decoupling of input frequency from oscillator Double balanced mixer with wide dynamic range and low-impedance inputs for the VHF, HYPER and UHF frequency range Internal band switch Internal low-noise reference voltage source Package TSSOP 28 Full ESD protection
s s
s s s s
Wireless Components
2-2
Specification, August 1999
TUA 6010XS
preliminary
Product Description
2.3 Application
s
The IC is suitable for all tuners in TV- and VCR-sets or cable set-top receivers for analog TV an Digital Video Broadcasting.
2.4 Package Outlines
P-TSSOP-28-1
Wireless Components
2-3
Specification, August 1999
3
Functional Description
Contents of this Chapter 3.1 3.2 3.3 3.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
TUA 6010XS
preliminary
Functional Description
3.1 Pin Configuration
MIXU MIXUx MIXV MIXVx VVCCA CAS IFout IFoutx GNDD SDA SCL VVCCD Q QX
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
OU-B2 OU-C1 OU-C2 OU-B1 OV-B2 OV-C1 OV-C2 OV-B1 GNDA TUNE CHGPMP P0 / I0 P1 / I1 P2 / ADC
TUA 6010XS
22 21 20 19 18 17 16 15
Pin_config.wmf
Figure 3-1
Pin Configuration
Wireless Components
3-2
Specification, August 1999
TUA 6010XS
preliminary
Functional Description
3.2 Pin Definition and Function
Table 3-1 Pin Definition and Function Pin No. Symbol Function UHF mixer input, low-impedance, symmetrical to MIXUx
1
MIXU
2
MIXUx
1 2
UHF mixer input, low-impedance, symmetrical to MIXU
3
MIXV
VHF or HYPER mixer input, low-impedance, symmetrical to MIXVx
4
MIXVx
3 4
VHF or HYPER mixer input, low-impedance, symmetrical to MIXV
5 6
VVCCA CAS
Positive supply voltage for analog block Chip address select
6
7
IFout
8
7
Open collector mixer output, high-impedance, symmetrical to IFoutx
8
IFoutx
Inverse open collector mixer output, highimpedance, symmetrical to IFout
9
GNDD
Digital Ground
Wireless Components
3-3
Specification, August 1999
TUA 6010XS
preliminary
Functional Description
10
SDA
Data input/output for the I2C bus
10
11
SCL
Clock input for the I2C bus
11
12
VVCCD
Positive supply voltage for digital block (PLL)
13
Q
13 14
4 MHz low-impedance crystal oscillator input
14
Qx
Inverse 4 MHz low-impedance crystal oscillator input
15
P2/ADC
15
Port output / ADC input
16
P1/I1
16
Port output / TTL input
Wireless Components
3-4
Specification, August 1999
TUA 6010XS
preliminary
Functional Description
17
P0/I0
17
Port output / TTL input
18
CHGPMP
Charge pump output / loop filter
18 19
19
TUNE
VCO tuning voltage output
20 21
GNDA OV-B1
Analog Ground VHF oscillator amplifier, high-impedance base input, symmetrical to OV-B2
22
OV-C2
VHF oscillator amplifier, high-impedance collector output, symmetrical to OV-C1
23
OV-C1
VHF oscillator amplifier, high-impedance collector output, symmetrical to OV-C2
21 22
23 24
24
OV-B2
VHF oscillator amplifier, high-impedance base input, symmetrical to OV-B1
Wireless Components
3-5
Specification, August 1999
TUA 6010XS
preliminary
Functional Description
25
OU-B1
UHF oscillator amplifier, high-impedance base input, symmetrical to OU-B2
26
OU-C2 UHF oscillator amplifier, high-impedance collector output, symmetrical to OU-C1
27
OU-C1 UHF oscillator amplifier, high-impedance collector output, symmetrical to OU-C2
28
OU-B2
25 26
27 28
UHF oscillator amplifier, high-impedance base input, symmetrical to OU-B1
Wireless Components
3-6
Specification, August 1999
TUA 6010XS
preliminary
Functional Description
3.3 Block Diagram
CHGPMP
GNDA
28
27
26
25
24
23
22
21
20
19
18
17
16
P2/ADC 15 fref 13 Qx 14
OU-C1
OU-C2
OU-B2
OU-B1
OV-C1
OV-C2
OV-B2
OV-B1
TUNE
Oscillator UHF
Oscillator VHF/HYP
VCO VCOx
PhaseDet.& ChgPmp
I/O-PORTS
Cy
Isolation Amplifier
Isolation Amplifier
Progr. Divider
Mixer UHF
Mixer VHF HYP
V/U
I2C-Bus Interface
Crystal Oscillator
1 MIXUx MIXU
2 MIXV
3 MIXVx
4 VVCCA
5 CAS
6 IFout
7 IFoutx
8 GNDD
9 SDA
10 SCL
11 VVCCD
12 Q
Figure 3-2
Block Diagram
Wireless Components
3-7
Specification, August 1999
P1/ I1
P0/IO
Ref.Divider
TUA 6010XS
preliminary
Functional Description
3.4 Circuit Description
3.4.1
Mixer-Oscillator block
The mixer oscillator section includes two balanced mixers (double balanced mixer), two balanced oscillators for VHF and/or HYPER and UHF, a reference voltage source and a band switch. Filters between tuner input and IC separate the TV frequency signals into two bands. The band switch ensures that only one mixer-oscillator block at a time is activated. In the activated band the signal passes a frontend stage with MOSFET amplifier, a double-tuned bandpass filter and is then fed to the balanced mixer input of the IC which has a low-impedance input. The input signal is mixed there with the on chip oscillator signal from the activated oscillator section.
3.4.2
PLL block
The mixer-oscillator signal VCO/VCOx is internally DC-coupled as a differential signal at the programmable divider inputs. The signal subsequently passes through a programmable divider with ratio N = 256 through 32767 and is then compared in a digital frequency / phase detector to a reference frequency fref = 62.5 kHz. This frequency is derived from a balanced, low-impedance 4 MHz crystal oscillator (pin Q, Qx) divided by Q = 64.
The phase detector has two outputs UP and DOWN that drive two current sources I+ and I- of a charge pump. If the negative edge of the divided VCO signal appears prior to the negative edge of the reference signal, the I+ current source pulses for the duration of the phase difference. In the reverse case the I- current source pulses. If the two signals are in phase, the charge pump output (CHGPMP) goes into the high-impedance state (PLL is locked). An active lowpass filter integrates the current pulses to generate the tuning voltage for the VCO (internal amplifier, external pullup resistor at TUNE and external RC circuitry). The charge pump output is also switched into the high-impedance state when the control bit T0 = 1. Here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of self-discharge in the peripheral circuity. TUNE may be switched off by the control bit OS to allow external adjustments. When the VCO is not working the PLL locks to a tuning voltage of 33V. By means of control bit 5I the pump current can be switched between two values by software. This programmability permits alteration of the control response of the PLL in the locked-in state. In this way different VCO gains can be compensated, for example.
Wireless Components
3-8
Specification, August 1999
TUA 6010XS
preliminary
Functional Description
The software-switched ports P0, P1, P2 are general-purpose open-collector outputs. The test bit T1 = 1, switches the test signals fref (4 MHz / 64) and Cy (divided input signal) to P0 and P1 respectively. P0, P1, P2 are bidirectional. The lock detector resets the lock flag FL when the width of the charge pump current pulses is greater than the period of the crystal oscillator (i.e. 250 ns). Hence, when FL = 1, the maximum deviation of the input frequency from the programmed frequency is given by f = IP (KVCO / fQ) (C1+C2) / (C1C2) where IP is the charge pump current, KVCO the VCO gain, fQ the crystal oscillator frequency and C1, C2 the capacitances in the loop filter (see application circuit). As the charge pump pulses at 62.5 kHz (= f ref), it takes a maximum of 16 s for FL to be reset after the loop has lost lock state. Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns for eight consecutive fref periods. Therefore it takes between 128 and 144 s for FL to be set after the loop regains lock.
3.4.3
I2C-Bus Interface
Data is exchanged between the processor and the PLL via the I2C bus. The clock is generated by the processor (input SCL), while pin SDA functions as an input or output depending on the direction of the data (open collector, external pull-up resistor). Both inputs have hysteresis and a low-pass characteristic, which enhance the noise immunity of the I2C bus. The data from the processor pass through an I2C bus controller. Depending on their function the data are subsequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are HIGH). Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH while SCL remains HIGH. All further information transfer takes place during SCL = LOW, and the data is forwarded to the control logic on the positive clock edge. The table 1 "bit allocation" should be referred to the following description. All telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which the control logic returns the SDA line to LOW (acknowledge condition). The first byte is comprised of seven address bits. These are used by the processor to select the PLL from several peripheral components (chip select). The LSB bit (R/W) determines whether data are written into (R/W = 0) or read from (R/W = 1) the PLL. In the data portion of the telegram during a WRITE operation, the MSB bit of the first or third data byte determines whether a divider ratio or control information is to follow. In each case the second byte of the same data type has to follow the first byte. If the address byte indicates a READ operation, the PLL generates an acknowledge and then shifts out the status byte onto the SDA line. If the processor generates an acknowledge, a further status byte is output; otherwise the data line
Wireless Components
3-9
Specification, August 1999
TUA 6010XS
preliminary
Functional Description
is released to allow the processor to generate a stop condition. The status word consists of two bits from the TTL input ports, three bits from the A/D converter, the lock flag and the power-on flag. Four different chip addresses can be set by appropriate connection of pin CAS (see table 2 "address selection"). When the supply voltage is applied, a power-on reset circuit prevents the PLL from setting the SDA line to LOW, which would block the bus. The power-on reset flag POR is set at power-on and when VVCCD goes below 3.2 V. It will be reset at the end of a READ operation.
Wireless Components
3 - 10
Specification, August 1999
4
Applications
Contents of this Chapter 4.1 4.2 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
TUA 6010XS
preliminary
Applications
4.1 Application Circuit
4.7n
+33V
1k BB639C
1k 4.7n 4.7n
82p 1k 2.2k 470p 3.3k BA 592 4.7p 4.7p BB639C 2.2p 100p 4.7n 22k 100k 1k 2.2k 4.7n 4.7k 33k
1.2p
1.2p
1.2p
1.2p
2.7p
2.2p
2.2p
2.7p
4.7n 22n
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TUA 6010XS
1 2
2.2p 22p 1 3 1:1 *) 6 4 6 22p 3 1n 1 220 1:1 *) 4 47p 27p 12p 220 4.7n 1n 4.7n 4.7n
3
4
5
6
7
47
8
9
10
11
12
13
14
4MHz 100p 100p 18p
UHF
VHF
VVCCA CAS
IF output
SDA SCL V VCCD
*) TOKO B4F Type 617DB-1023
Figure 4-1 Evaluation Board
Wireless Components
4-2
Specification, August 1999
TUA 6010XS
preliminary
Applications
4.2 Hints
See separate available Application Note TUA 6010XS.
Wireless Components
4-3
Specification, August 1999
5
Reference
Contents of this Chapter 5.1 5.1.1 5.1.2 5.1.3 5.2 5.3 5.4 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Bit Allocation Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
TUA 6010XS
preliminary
Reference
5.1 Electrical Data
5.1.1
Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-20C ... + 80C Parameter Symbol Limit Values min PLL Supply voltage CHGPMP Crystal oscillator pins Q, Qx Bus input/output SDA Bus output current SDA Bus input SCL Port outputs P0, P1, P2 Chip address switch CAS VCO tuning output (loop filter) Bus output SDA Port outputs P0, P1, P2 Total port output current Junction temperature Storage temperature Thermal resistance (junction to ambient) VVCCD VCHGPMP ICHGPMP VQ IQ VSDA ISDA(L) VSCL VP VCAS VTUNE ISDAL IP(L) IP(L) TJ TStg RthSA -40 -0.3 -0.3 1 VVCCD -5 -0.3 -0.3 -0.3 -0.3 -0.3 -1 -1 +6 5 +6 +13 VVCCD +35 5 15 20 +125 +125 130 +6 V V mA V mA V mA V V V V mA mA mA C C K/W open collector open collector tmax = 0,1 sec. at 6 V max Unit Remarks
Wireless Components
5-2
Specification, August 1999
TUA 6010XS
preliminary
Reference
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-20C ... + 80C (continued) Parameter Symbol Limit Values min Mixer-Oscillator Supply voltage Mix inputs VHF/UHF VCO base voltage VCO collector voltage IF output VVCCA VMIX V/U IMIX V/U VOU-B/OV-B VOU-C/OV-C VIFout VIFoutx -0.3 -5 -0.3 +6 2 6 3 VVCCA 6 V V mA V V V max Unit Remarks
All values are referred to ground (pin), unless stated otherwise. Currents with a positive sign flows into the pin and currents with a negative sign flows out of pin.
ESD-Protection* all pins unless otherwise specified Mixer inputs MIXU / MIXV Mixer outputs IFout / IFoutx Ports Charge pump VESD VESD MIX VESD IF VESD P VESD CP -1 -500 -500 -500 -500 1 500 500 500 500 kV V V V V Pin 1, 2, 3, 4 Pin 7, 8 Pin 15, 16, 17 Pin 18
*according to MIL STD 883D, method 3015.7 and EOS/ESD assn. standard S5.1 - 1993
5.1.2
Operating Range
Within the operational range the IC operates as described in the circuit description. The AC / DC characteristic limits are not guaranteed.
Table 5-2 Operating Range Parameter Symbol Limit Values min Supply voltage Supply voltage Mixer output voltage Programmable divider factor VHF Mixer input frequency range UHF Mixer input frequency range VHF Oscillator frequency range UHF Oscillator frequency range Ambient temperature VVCCD VVCCA VIFout VIFoutx N fMIXV fMIXU fOV fOU Tamb +4.5 +4.5 +4.5 256 30 400 30 400 -20 max +5.5 +5.5 +5.5 32767 500 900 500 900 +80 MHz MHz MHz MHz C V V V open collector Unit Test Conditions L Item
Wireless Components
5-3
Specification, August 1999
TUA 6010XS
preliminary
Reference
5.1.3
AC/DC Characteristics
Table 5-3 AC/DC Characteristics with Tamb 25 C, VVCCA = 5 V, VVCCD = 5 V Symbol min Limit Values typ max Unit Test Conditions L Item
Digital Unit
PLL Supply current IVCCD 19 24 29 mA VVCCD = 5 V 1.1
Crystal oscillator connections Q, Qx Crystal frequency Crystal resistance Oscillation frequency Input impedance Margin from 1st (fundamental) to 2nd and 3rd harmonics fQ RQ fQ ZQ aH 3.2 10 3,99975 -600 20 4,000 -750 4.0 4.8 100 4,00025 -900 MHz MHz dB series resonance series resonance fQ = 4 MHz fQ = 4 MHz fQ = 4 MHz
Charge pump output CHGPMP HIGH output current LOW output current Tristate current Output voltage ICPH ICPL ICPZ VCP 1.0 90 22 220 50 +1 2.5 300 75 A A nA V 5I = 1, VCP = 2 V 5I = 0, VCP = 2 V T0 = 1, VCP = 2 V locked
Drive output TUNE (open collector) HIGH output current LOW output voltage I2C-Bus Bus inputs SCL, SDA HIGH input voltage LOW input voltage HIGH input current LOW input current VIH VIL IIH IIL -10 3 0 5.5 1.5 10 V V A A A V VIH = VS VIL = 0 V ITH VTL 10 0.5 A V VTH = 33 V, T0 = 1 ITL = 1.0 mA 1.2
Bus output SDA (open collector) HIGH output current LOW output voltage Edge speed SCL,SDA Rise time Fall time tr tf 300 300 ns ns IOH VOL 10 0.4 VOH = 5.5 V IOL = 3 mA
Wireless Components
5-4
Specification, August 1999
TUA 6010XS
preliminary
Reference
Table 5-3 AC/DC Characteristics with Tamb 25 C, VVCCA = 5 V, VVCCD = 5 V (Continued) Symbol min Clock timing SCL Frequency HIGH pulse width LOW pulse width Start condition Set-up time Hold time Stop condition Set up time Bus free Data transfer Set-up time Hold time Input hysteresis SCL, SDA (1) Pulse width of spikes which are suppressed Capacitive load for each bus line tsudat thdat Vhys tsp CL 0 0.1 0 200 50 400 s s mV ns pF tsusto tbuf 0.6 1.3 s s tsusta thsta 0.6 0.6 s s fSCL tH tL 0 0.6 1.3 400 kHz s s Limit Values typ max Unit Test Conditions L Item
Port outputs P0, P1, P2 (open collector) HIGH output current LOW output voltage TTL port inputs P0, P1 HIGH input voltage LOW input voltage HIGH input current LOW input current ADC port input P2 HIGH input current LOW input current IADCH IADCL -10 10 A A A A VPIH VPIL IPIH IPIL -10 2.7 0.8 10 V V A A VPIH = 13.5 V VPIL = 0 V IPOH VPOL 1 0.5 A V VPOH = 5 V IPOL = 15 mA
Address selection input CAS HIGH input current LOW input current ICASH ICASL -50 50 VCASH = 5 V VCASL = 0 V
Wireless Components
5-5
Specification, August 1999
TUA 6010XS
preliminary
Reference
Table 5-3 AC/DC Characteristics with Tamb 25 C, VVCCA = 5 V, VVCCD = 5 V (Continued) Symbol min Limit Values typ max Unit Test Conditions L Item
Analog Unit
Mixer-Oscillator Current consumption IVCCA IVCCA Mixer current Mixer output impedance IIF-V/IF-U RIFout,IF outx CIFout,IF outx VHF and Hyper Band Section Oscillator frequency range fOscV fOscH Oscillator drift fOscV fOscV fOscV Oscillator pulling VMIXV VMIXV VMIXV VMIXV Oscillator phase noise Mixer gain Mixer noise figure L(fm)VH
F
2.1 11 14 4 15 18 6 20 19 22 8 mA mA mA k Parallel equivalent circuit, fIF = 38,9 MHz Parallel equivalent circuit, fIF = 38,9 MHz 2.2 80 140 170 450 400 500 100 100 100 80 80 -80 11 108 108 88 88 -86 14 5 5 150 1000 17 8 8 MHz MHz kHz kHz kHz dBV dBV dBV dBV dBc/ Hz dB dB dB mVrms Channel E2 (DSB) Channel 10 (DSB) max. input level for 10 dB distance fin/LO Vd = 0,5..28 V; VHF Vd = 0,5..28 V; HYP VS = 5 V10% T = 25 C t = 5 s up to 15 min after switching on f = 10 kHz in channel E2 f = 10 kHz in channel S10 fint = E2 + N + 5 1 MHz fint = S10 + N + 5 1 MHz fm = 10 kHz, application circuit Bit V/U = Low Bit V/U = High
0.5
pF
GMixV FMixV FMixV
Crosstalk fin/LO
VMixV
Wireless Components
5-6
Specification, August 1999
TUA 6010XS
preliminary
Reference
Table 5-3 AC/DC Characteristics with Tamb 25 C, VVCCA = 5 V, VVCCD = 5 V (Continued) Symbol min Mixer input impedance RMixV Limit Values typ 20 max W serial equivalent circuit, fMixV = 300 MHz serial equivalent circuit, fMixV = 300 MHz VMixB = 80 dBV 2.3 fOscU fOscU fOscU fOscU Oscillator pulling VMIXU VMIXU VMIXU VMIXU Oscillator phase noise Mixer gain Mixer noise figure L(fm)UH
F
Unit
Test Conditions
L
Item
LMixV
10
nH
IF suppression UHF Section Oscillator frequency range Oscillator drift
aIF
20
dB
440
900 400 800 100
MHz kHz kHz kHz dBV dBV dBV dBV dBc/ Hz
Vt = 0,5...28 V VS = 5 V10% T = 25 C t = 5 s up to 15 min after switching on f = 10 kHz in channel E21 f = 10 kHz in channel E68 fint = E21 + N + 5 1 MHz fint = E68 + N + 5 1 MHz fm = 10 kHz, application circuit
100 100 80 80 -80 11
108 108 88 88 -86 14 6 7 17 9 10
GMixU FMixU
dB dB dB mVrms Channel E21 (DSB) Channel E68 (DSB) max. input level for 10 dB distance fin/LO serial equivalent circuit, fMixU = 600 MHz serial equivalent circuit, fMixU = 600 MHz VMixB = 80 dBV
Crosstalk fin/LO
VMixU
150
1000
Mixer input impedance
RMixU
20
W
LMixU
10
nH
IF suppression
aIF
20
dB
s This value is only guaranteed in lab.
Wireless Components
5-7
Specification, August 1999
TUA 6010XS
preliminary
Reference
5.2 Bit Allocation Read / Write
Table 5-4 Byte Write Data Address Byte Progr. Divider Byte 1 Progr. Divider Byte 2 Control Byte 1 Control Byte 2 Read Data Address Byte Status Byte 1 POR 1 FL 0 x 0 I1 0 I0 MA1 A2 MA0 A1 1 A0 A A 1 0 n7 1 V/U 1 n14 n6 5I x 0 n13 n5 T1 x 0 n12 n4 T0 x 0 n11 n3 1 x MA1 n10 n2 1 P2 MA0 n9 n1 1 P1 0 n8 n0 OS P0 A A A A A MSB*) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 LSB Ack Remarks
*) MSB shifted first.
Divider ratio: N = 16384 x n14 + 8192 x n13 + 4096 x n12 + 2048 x n11 + 1024 x n10 + 512 x n9 + 256 x n8 +128 x n7 + 64 x n6 + 32 x n5 + 16 x n4 + 8 x n3 + 4 x n2 + 2 x n1 + n0
Control Bytes:
s
Ports P0, P1, P2: open-collector output is active open-collector output is inactive, TTL-inputs I1, I0 and ADC available
P0...P2=1 P0...P2=0
s
Bandswitch V/U: switch to OSC/MIX UHF switch to OSC/MIX VHF
V/U=1 V/U=0
s
Pump current 5I: high PD output current low PD output current
5I=1 5I=0
s
Disabling tuning voltage OS: disables TUNE enables TUNE
OS=1 OS=0
Wireless Components
5-8
Specification, August 1999
TUA 6010XS
preliminary
Reference
Status Byte:
s
Power On Reset flag POR:
flag is set at power-on and reset at the end of READ operation
s
PLL lock flag FL:
flag is set to 1 when loop is locked
s
TTL-inputs I1, I0:
input data from pins P1/I1, P0/I0
s
ADC bits A2,A1,A0:
digital outputs of the 5-level ADC
Table 5-5 Address Selection Voltage at CAS (0...0.1) * VVCC open circuit (0.4...0.6) * VVCC (0.9...1) * VVCC MA1 0 0 1 1 MA0 0 1 0 1
Table 5-6 Test Modes Test mode Normal operation P1 = Cy output, P0 = fref output Charge pump output, CHGPMP is in high-impedance state TTL-inputs I1/I0 are Cy/fref inputs of phase detector T1 0 1 0 1 T0 0 0 1 1
Table 5-7 A/D Converter Levels
Voltage at P2 / ADC
(0...0.15) * VVCC (0.15...0.3) * VVCC (0.3...0.45) * VVCC (0.45...0.6) * VVCC (0.6...1) * VVCC
A2
0 0 0 0 1
A1
0 0 1 1 0
A0
0 1 0 1 0
Wireless Components
5-9
Specification, August 1999
Wireless Components
Addressing
Ack.
1st Byte
Ack.
2nd Byte
Ack.
3rd Byte
Ack. 4th Byte
MA MA
R/W
5.3 I2C Bus Timing Diagram
5 - 10
Note: SDA
SCL
Telegram examples: Start Addr DR1 DR2 CW1 CW2 Stop = start condition = address byte = prog. divider byte 1 = prog. divider byte 2 = control byte 1 = control byte 2 = stop condition Reference
preliminary
Start-Addr-DR1-DR2-CW1-CW2-Stop Start-Addr-CW1-CW2-DR1-DR2-Stop Start-Addr-DR1-DR2-Stop Start-Addr-CW1-CW2-Stop
TUA 6010XS
Specification, August 1999
TUA 6010XS
preliminary
Reference
5.4 Test Circuits
1n
+33V
33k
BB639C
33k 4.7n 470n
82p 1k 33k 33k 470p 1n 3.3k BB639C BA 592 2.2p 4.7p 5.6p 100p 10n 12k 100k 1.2p 1.2p 1.2p 1.2p 2.2p 2.2p 2.2p 2.2p 56n 39k 1k 1k 100p
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TUA 6010XS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
22p 2 4 SMT4 1:1 5
22p 2
1n 4 SMT4 1:1 5
1n 4.7n
22p 10
22p
100p 100 100 470n
18p
33p 1 1 1n
IF output UHF VHF VVCCA CAS
SDA SCL V VCCD
Figure 5-1
DC and RF Parameter Measurement
Wireless Components
5 - 11
Specification, August 1999
TUA 6010XS
preliminary
Reference
Test mode: VVCC IVCC Q 18 pF 4 MHz P0 TUA 6010XS 5k P1 fcy GNDD Counter 5V
T1 = HIGH T0 = LOW
5k
fref Counter
fQ = fref * 64
fVCO = fcy * N N: divider ratio
Figure 5-2
Measurement of Crystal Oscillator Frequency
Wireless Components
5 - 12
Specification, August 1999

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